Watchdog Timer WDT (Special Considerations)
The watchdog timer operates asynchronously (it has its own clock) to the rest of the system. The watchdog timer reset instruction is therefore repeatedly issued in stopped mode to avoid false resets if the watchdog timer is enabled. Debugging the exact timing of the WDT behavior while doing single stepping or when stopping the program execution, is therefore not supported by the ICE200.

Disabling WDT is secured by the WDTTOE (WDT turn-off enable) bit. Following is an assembly program example that shows an WDT disable sequence: 

disableWDT:
   ldi  r16, (1<<WDTTOE) ; Set the WDT turn-off enable bit
  (cli)                  ; (only needed if any interrupts are in use)
   out  WDTCR, r16
   ldi  r16, (1<<WDE)    ; Within 4 cycles, clear the WDE bit
   out WDTCR, r16
done:
  (sei)                  ; (only needed if any interrupts are in use)


The four cycle time-out for the WDT disabling is not supported by the AT90EM04 when in stopped mode. This means that single stepping this sequence will not disable the WDT.

Tip!
You can use the run to cursor to the instruction after the WDT enable bit is cleared (labeled done in the example above), instead of doing single stepping. Or use the following macro (for AVR Assembler only).

MACRO: 

.macro disableWDT
   ldi  r16, (1<<WDTTOE)
  (cli)
   out  WDTCR, r16
   ldi  r16, (0<<WDE)
   out  WDTCR, r16
  (sei )
.endmacro
USAGE: 
   disableWDT


See Also