AVR Studio: Contents of Trace Buffer

Contents of Trace buffer based on instruction

As can be seen from the previous section, the contents of the different columns varies with which instruction is being executed. This section describes how to interpret the contents of the Trace buffer based on which instruction is being executed.

All the explanations are tagged with a number. This number indicates the cycle number in the instruction execution (important for multi-cycle instructions only). The term N/A is used when a field does not contain any valuable information.

Arithmetic and Logic Instructions

Instruction PMem Addr Reg.Val Dat.Addr Dat.Val

ADD Rd,Rr Address of instruction Result of addition N/A N/A

ADC Rd,Rr Address of instruction Result of addition N/A N/A

SUB Rd,Rr Address of instruction Result of subtraction N/A N/A

SUBI Rd,K Address of instruction Result of subtraction N/A N/A

SBC Rd,Rr Address of instruction Result of subtraction N/A N/A

SBCI Rd,K Address of instruction Result of subtraction N/A N/A

AND Rd,Rr Address of instruction Result of logical AND N/A N/A

ANDI Rd,K Address of instruction Result of logical AND N/A N/A

OR Rd,Rr Address of instruction Result of logical OR N/A N/A

ORI Rd,K Address of instruction Result og logical OR N/A N/A

EOR Rd,Rr Address of instruction Result of logical EOR N/A N/A

COM Rd Address of instruction Result of complement N/A N/A

NEG Rd Address of instruction Result of negation N/A N/A

SBR Rd Will never appear (is disassembled to ORI instruction) N/A N/A N/A

CBR Rd Will never appear (is disassembled to ANDI instruction) N/A N/A N/A

INC Rd Address of instruction Result of incrementation N/A N/A

DEC Rd Address of instruction Result of decrementation N/A N/A

TST Rd Will never appear (is disassembled to AND instruction) N/A N/A N/A

CLR Rd Address of instruction Result (always 0x00) N/A N/A

SER Rd Will never appear (is disassembled to LDI instruction) N/A N/A N/A

ADIW Rdl,K 1. Address of instruction
2. Address of next instruction 1. Result of addition, low byte
2. Result of addition, high byte 1. N/A
2. N/A 1. N/A
2. N/A

SBIW Rdl,K 1. Address of instruction
2. Address of next instruction 1. Result of subtraction, low byte
2. Result of subtraction, high byte 1. N/A
2. N/A 1. N/A
2. N/A

MUL Rd,Rr Currently not supported in Emulator N/A N/A N/A

MULS Rd,Rr Currently not supported in Emulator N/A N/A N/A

MULSU Rd,Rr Currently not supported in Emulator N/A N/A N/A

FMUL Rd,Rr Currently not supported in Emulator N/A N/A N/A

FMULS Rd,Rr Currently not supported in Emulator N/A N/A N/A

FMULSU Rd,Rr Currently not supported in Emulator N/A N/A N/A

Instruction	PMem Addr	Reg.Val	Dat.Addr	Dat.Val
ADD Rd,Rr	Address of instruction	Result of addition	N/A	N/A
ADC Rd,Rr	Address of instruction	Result of addition	N/A	N/A
SUB Rd,Rr	Address of instruction	Result of subtraction	N/A	N/A
SUBI Rd,K	Address of instruction	Result of subtraction	N/A	N/A
SBC Rd,Rr	Address of instruction	Result of subtraction	N/A	N/A
SBCI Rd,K	Address of instruction	Result of subtraction	N/A	N/A
AND Rd,Rr	Address of instruction	Result of logical AND	N/A	N/A
ANDI Rd,K	Address of instruction	Result of logical AND	N/A	N/A
OR Rd,Rr	Address of instruction	Result of logical OR	N/A	N/A
ORI Rd,K	Address of instruction	Result og logical OR	N/A	N/A
EOR Rd,Rr	Address of instruction	Result of logical EOR	N/A	N/A
COM Rd	Address of instruction	Result of complement	N/A	N/A
NEG Rd	Address of instruction	Result of negation	N/A	N/A
SBR Rd	Will never appear (is disassembled to ORI instruction)	N/A	N/A	N/A
CBR Rd	Will never appear (is disassembled to ANDI instruction)	N/A	N/A	N/A
INC Rd	Address of instruction	Result of incrementation	N/A	N/A
DEC Rd	Address of instruction	Result of decrementation	N/A	N/A
TST Rd	Will never appear (is disassembled to AND instruction)	N/A	N/A	N/A
CLR Rd	Address of instruction	Result (always 0x00)	N/A	N/A
SER Rd	Will never appear (is disassembled to LDI instruction)	N/A	N/A	N/A
ADIW Rdl,K	1. Address of instruction 2. Address of next instruction	1. Result of addition, low byte 2. Result of addition, high byte	1. N/A 2. N/A	1. N/A 2. N/A
SBIW Rdl,K	1. Address of instruction 2. Address of next instruction	1. Result of subtraction, low byte 2. Result of subtraction, high byte	1. N/A 2. N/A	1. N/A 2. N/A
MUL Rd,Rr	Currently not supported in Emulator	N/A	N/A	N/A
MULS Rd,Rr	Currently not supported in Emulator	N/A	N/A	N/A
MULSU Rd,Rr	Currently not supported in Emulator	N/A	N/A	N/A
FMUL Rd,Rr	Currently not supported in Emulator	N/A	N/A	N/A
FMULS Rd,Rr	Currently not supported in Emulator	N/A	N/A	N/A
FMULSU Rd,Rr	Currently not supported in Emulator	N/A	N/A	N/A

Branch Instructions

Instruction PMem Addr Reg.Val Dat.Addr Dat.Val

RJMP k 1. Address of instruction 2. N/A 1. N/A
2. N/A 1. N/A
2. N/A 1. N/A
2. N/A

IJMP 1. Address of instruction 2. N/A 1. N/A
2. N/A 1. N/A
2. Destination address 1. N/A
2. N/A

EIJMP Currently not supported in Emulator N/A N/A N/A

JMP k 1. Address of instruction 2. Address of address-part of instruction
3. N/A 1. N/A
2. N/A
3. N/A 1. N/A
2. N/A
3. N/A 1. N/A
2. N/A
3. N/A

RCALL k Stack in internal memory:
1. Address of instruction
2. N/A
3. Address of RCALL destination Stack in internal memory:
1. N/A
2. N/A
3. N/A Stack in internal memory:
1. N/A
2. Stack Pointer
3. Stack Pointer Stack in internal memory:
1. N/A
2. Return address, low byte
3. Return address, high byte

ICALL Stack in internal memory:
1. Address of instruction
2. N/A
3. Address of ICALL destination Stack in internal memory:
1. N/A
2. N/A
3. N/A Stack in internal memory:
1. N/A
2. Stack Pointer
3. Stack Pointer Stack in internal memory:
1. N/A
2. Return address, low byte
3. Return address, high byte

EICALL Currently not supported in Emulator N/A N/A N/A

CALL k Stack in internal memory:
1. Address of instruction
2. Address of address-part of instruction
3. N/A
4. Address of CALL destination Stack in internal memory:
1. N/A
2. N/A
3. N/A
4. N/A Stack in internal memory:
1. N/A
2. N/A
3. Stack Pointer
4. Stack Pointer Stack in internal memory:
1. N/A
2. N/A
3. Return address, low byte
4. Return address, high byte

RET Stack in internal memory:
1. Address of instruction
2. N/A
3. N/A
4. N/A Stack in internal memory:
1. N/A
2. N/A
3. N/A
4. N/A Stack in internal memory:
1. N/A
2. Stack Pointer
3. Stack Pointer
4. N/A Stack in internal memory:
1. N/A
2. Return address, high byte
3. Return address, low byte
4. N/A

RETI Stack in internal memory:
1. Address of instruction
2. N/A
3. N/A
4. N/A Stack in internal memory:
1. N/A
2. N/A
3. N/A
4. N/A Stack in internal memory:
1. N/A
2. Stack Pointer
3. Stack Pointer
4. N/A Stack in internal memory:
1. N/A
2. Return address, high byte
3. Return address, low byte
4. N/A

CPSE Rd,Rr Condition not met (no skip)
1. Address of instruction
Condition met, skipping 1 word instruction
1. Address of instruction
2. Address of skipped instruction
Condition met, skipping 2 word instruction
1. Address of instruction
2. Address of skipped instruction, first word
3. Address of skipped instruction, second word
Condition not met (no skip)
1. N/A
Condition met, skipping 1 word instruction
1. N/A
2. N/A
Condition met, skipping 2 word instruction
1. N/A
2. N/A
3. N/A
Condition not met (no skip)
1. N/A
Condition met, skipping 1 word instruction
1. N/A
2. N/A
Condition met, skipping 2 word instruction
1. N/A
2. N/A
3. N/A
Condition not met (no skip)
1. N/A
Condition met, skipping 1 word instruction
1. N/A
2. N/A
Condition met, skipping 2 word instruction
1. N/A
2. N/A
3. N/A

CP Rd,Rr Address of instruction N/A N/A N/A

CPC Rd,Rr Address of instruction N/A N/A N/A

CPI Rd,K Address of instruction N/A N/A N/A

SBRC Rr,b Condition not met (no skip)
1. Address of instruction
Condition met, skipping 1 word instruction
1. Address of instruction
2. Address of skipped instruction
Condition met, skipping 2 word instruction
1. Address of instruction
2. Address of skipped instruction, first word
3. Address of skipped instruction, second word
Condition not met (no skip)
1. Value of register
Condition met, skipping 1 word instruction
1. Value of register
2. N/A
Condition met, skipping 2 word instruction
1. Value of register
2. N/A
3. N/A
Condition not met (no skip)
1. N/A
Condition met, skipping 1 word instruction
1. N/A
2. N/A
Condition met, skipping 2 word instruction
1. N/A
2. N/A
3. N/A
Condition not met (no skip)
1. N/A
Condition met, skipping 1 word instruction
1. N/A
2. N/A
Condition met, skipping 2 word instruction
1. N/A
2. N/A
3. N/A

SBRS Rr,b Condition not met (no skip)
1. Address of instruction
Condition met, skipping 1 word instruction
1. Address of instruction
2. Address of skipped instruction
Condition met, skipping 2 word instruction
1. Address of instruction
2. Address of skipped instruction, first word
3. Address of skipped instruction, second word
Condition not met (no skip)
1. Value of register
Condition met, skipping 1 word instruction
1. Value of register
2. N/A
Condition met, skipping 2 word instruction
1. Value of register
2. N/A
3. N/A
Condition not met (no skip)
1. N/A
Condition met, skipping 1 word instruction
1. N/A
2. N/A
Condition met, skipping 2 word instruction
1. N/A
2. N/A
3. N/A
Condition not met (no skip)
1. N/A
Condition met, skipping 1 word instruction
1. N/A
2. N/A
Condition met, skipping 2 word instruction
1. N/A
2. N/A
3. N/A

SBIC A,b Condition not met (no skip)
1. Address of instruction
Condition met, skipping 1 word instruction
1. Address of instruction
2. Address of skipped instruction
Condition met, skipping 2 word instruction
1. Address of instruction
2. Address of skipped instruction, first word
3. Address of skipped instruction, second word
Condition not met (no skip)
1. N/A
Condition met, skipping 1 word instruction
1. N/A
2. N/A
Condition met, skipping 2 word instruction
1. N/A
2. N/A
3. N/A
Condition not met (no skip)
1. 5 LSB give I/O address (A)
Condition met, skipping 1 word instruction
1. 5 LSB give I/O address (A)
2. N/A
Condition met, skipping 2 word instruction
1. 5 LSB give I/O address (A)
2. N/A
3. N/A
Condition not met (no skip)
1. N/A
Condition met, skipping 1 word instruction
1. N/A
2. N/A
Condition met, skipping 2 word instruction
1. N/A
2. N/A
3. N/A

SBIS A,b Condition not met (no skip)
1. Address of instruction
Condition met, skipping 1 word instruction
1. Address of instruction
2. Address of skipped instruction
Condition met, skipping 2 word instruction
1. Address of instruction
2. Address of skipped instruction, first word
3. Address of skipped instruction, second word
Condition not met (no skip)
1. N/A
Condition met, skipping 1 word instruction
1. N/A
2. N/A
Condition met, skipping 2 word instruction
1. N/A
2. N/A
3. N/A
Condition not met (no skip)
1. 5 LSB give I/O address (A)
Condition met, skipping 1 word instruction
1. 5 LSB give I/O address (A)
2. N/A
Condition met, skipping 2 word instruction
1. 5 LSB give I/O address (A)
2. N/A
3. N/A
Condition not met (no skip)
1. N/A
Condition met, skipping 1 word instruction
1. N/A
2. N/A
Condition met, skipping 2 word instruction
1. N/A
2. N/A
3. N/A

BRBC s,k Will never appear (is disassembled to other branch instructions) N/A N/A N/A

BRBS s,k Will never appear (is disassembled to other branch instructions) N/A N/A N/A

BREQ k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRNE k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRCS k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRCC k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRSH k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRLO k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRMI k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRPL k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRGE k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRLT k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRHS k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRHC k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRTS k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRTC k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRVS k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRVC k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRIE k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

BRID k Branch not taken:
1. Address of instruction
Branch taken:
1. Address of instruction
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A
Branch not taken:
1. N/A
Branch taken:
1. N/A
2. N/A

Data Transfer Instructions

Instruction PMem Addr Reg.Val Dat.Addr Dat.Val

MOV Rd,Rr Address of instruction Value loaded into register N/A N/A

MOVW Rd,Rr Currently not supported in Emulator N/A N/A N/A

LDI Rd,K Address of instruction Value loaded into register N/A N/A

LDS Rd,k Internal memory:
1. Address of instruction
2. Address of address-part of instruction Internal memory:
1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (k) Internal memory:
1. N/A
2. Value read

LD Rd,X Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory: 1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (X) Internal memory:
1. N/A
2. Value read

LD Rd,X+ Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (X) Internal memory:
1. N/A Value read

LD Rd,-X Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (X) Internal memory:
1. N/A
2. Value read

LD Rd,Y Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (Y) Internal memory:
1. N/A
2. Value read

LD Rd,Y+ Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (Y) Internal memory:
1. N/A
2. Value read

LD Rd,-Y Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (Y) Internal memory:
1. N/A
2. Value read

LDD Rd,Y+q Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (Y+q) Internal memory:
1. N/A
2. Value read

LD Rd,Z Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (Z) Internal memory:
1. N/A
2. Value read

LD Rd,Z+ Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (Z) Internal memory:
1. N/A
2. Value read

LD Rd,-Z Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (Z) Internal memory:
1. N/A
2. Value read

LDD Rd,Z+q Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value read Internal memory:
1. N/A
2. Address read from (Z+q) Internal memory:
1. N/A
2. Value read

STS k,Rr Internal memory:
1. Address of instruction
2. Address of address-part of instruction Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (k) Internal memory:
1. N/A
2. Value written

ST X,Rr Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (X) Internal memory:
1. N/A
2. Value written

ST X+,Rr Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (X) Internal memory:
1. N/A
2. Value written

ST -X,Rr Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (X) Internal memory:
1. N/A
2. Value written

ST Y,Rr Internal memory:
1. Address of instruction
2. Address of next instructio Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (Y) Internal memory:
1. N/A
2. Value written

ST Y+,Rr Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (Y) Internal memory:
1. N/A
2. Value written

ST -Y,Rr Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (Y) Internal memory:
1. N/A
2. Value written

STD Y+q,Rr Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (Y+q) Internal memory:
1. N/A
2. Value written

ST Z,Rr Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (Z) Internal memory:
1. N/A
2. Value written

ST Z+,Rr Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (Z) Internal memory:
1. N/A
2. Value written

ST -Z,Rr Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (Z) Internal memory:
1. N/A
2. Value written

STD Z+q,Rr Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. N/A Internal memory:
1. N/A
2. Address written to (Z+q) Internal memory:
1. N/A
2. Value written

LPM 1. Address of instruction
2. Address of next instruction
3. Word address of data read 1. NA
2. N/A
3. Data read 1. N/A
2. N/A
3. N/A 1. N/A
2. N/A
3. N/A

LPM Rd,Z Currently not supported in Emulator N/A N/A N/A

LPM Rd,Z+ Currently not supported in Emulator N/A N/A N/A

ELPM 1. Address of instruction
2. Address of next instruction
3. Word address of data read 1. N/A
2. N/A
3. Data read 1. N/A
2. N/A
3. N/A 1. N/A
2. N/A
3. N/A

ELPM Rd,Z Currently not supported in Emulator N/A N/A N/A

ELPM Rd,Z+ Currently not supported in Emulator N/A N/A N/A

SPM Currently not supported in Emulator N/A N/A N/A

ESPM Currently not supported in Emulator N/A N/A N/A

IN Rd,A Address of instruction Value read from port 6 LSB give I/O address (A) Value read from port

OUT A,Rr Address of instruction Value written to port 6 LSB give I/O address (A) Value written to port

PUSH Rr Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value pushed Internal memory:
1. N/A
2. Stack Pointer Internal memory:
1. N/A
2. Value pushed

POP Rd Internal memory:
1. Address of instruction
2. Address of next instruction Internal memory:
1. N/A
2. Value popped Internal memory:
1. N/A
2. Stack Pointer Internal memory:
1. N/A
2. Value popped

Instruction	PMem Addr	Reg.Val	Dat.Addr	Dat.Val
MOV Rd,Rr	Address of instruction	Value loaded into register	N/A	N/A
MOVW Rd,Rr	Currently not supported in Emulator	N/A	N/A	N/A
LDI Rd,K	Address of instruction	Value loaded into register	N/A	N/A
LDS Rd,k	Internal memory: 1. Address of instruction 2. Address of address-part of instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (k)	Internal memory: 1. N/A 2. Value read
LD Rd,X	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (X)	Internal memory: 1. N/A 2. Value read
LD Rd,X+	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (X)	Internal memory: 1. N/A Value read
LD Rd,-X	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (X)	Internal memory: 1. N/A 2. Value read
LD Rd,Y	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (Y)	Internal memory: 1. N/A 2. Value read
LD Rd,Y+	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (Y)	Internal memory: 1. N/A 2. Value read
LD Rd,-Y	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (Y)	Internal memory: 1. N/A 2. Value read
LDD Rd,Y+q	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (Y+q)	Internal memory: 1. N/A 2. Value read
LD Rd,Z	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (Z)	Internal memory: 1. N/A 2. Value read
LD Rd,Z+	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (Z)	Internal memory: 1. N/A 2. Value read
LD Rd,-Z	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (Z)	Internal memory: 1. N/A 2. Value read
LDD Rd,Z+q	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value read	Internal memory: 1. N/A 2. Address read from (Z+q)	Internal memory: 1. N/A 2. Value read
STS k,Rr	Internal memory: 1. Address of instruction 2. Address of address-part of instruction	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (k)	Internal memory: 1. N/A 2. Value written
ST X,Rr	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (X)	Internal memory: 1. N/A 2. Value written
ST X+,Rr	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (X)	Internal memory: 1. N/A 2. Value written
ST -X,Rr	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (X)	Internal memory: 1. N/A 2. Value written
ST Y,Rr	Internal memory: 1. Address of instruction 2. Address of next instructio	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (Y)	Internal memory: 1. N/A 2. Value written
ST Y+,Rr	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (Y)	Internal memory: 1. N/A 2. Value written
ST -Y,Rr	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (Y)	Internal memory: 1. N/A 2. Value written
STD Y+q,Rr	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (Y+q)	Internal memory: 1. N/A 2. Value written
ST Z,Rr	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (Z)	Internal memory: 1. N/A 2. Value written
ST Z+,Rr	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (Z)	Internal memory: 1. N/A 2. Value written
ST -Z,Rr	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (Z)	Internal memory: 1. N/A 2. Value written
STD Z+q,Rr	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. N/A	Internal memory: 1. N/A 2. Address written to (Z+q)	Internal memory: 1. N/A 2. Value written
LPM	1. Address of instruction 2. Address of next instruction 3. Word address of data read	1. NA 2. N/A 3. Data read	1. N/A 2. N/A 3. N/A	1. N/A 2. N/A 3. N/A
LPM Rd,Z	Currently not supported in Emulator	N/A	N/A	N/A
LPM Rd,Z+	Currently not supported in Emulator	N/A	N/A	N/A
ELPM	1. Address of instruction 2. Address of next instruction 3. Word address of data read	1. N/A 2. N/A 3. Data read	1. N/A 2. N/A 3. N/A	1. N/A 2. N/A 3. N/A
ELPM Rd,Z	Currently not supported in Emulator	N/A	N/A	N/A
ELPM Rd,Z+	Currently not supported in Emulator	N/A	N/A	N/A
SPM	Currently not supported in Emulator	N/A	N/A	N/A
ESPM	Currently not supported in Emulator	N/A	N/A	N/A
IN Rd,A	Address of instruction	Value read from port	6 LSB give I/O address (A)	Value read from port
OUT A,Rr	Address of instruction	Value written to port	6 LSB give I/O address (A)	Value written to port
PUSH Rr	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value pushed	Internal memory: 1. N/A 2. Stack Pointer	Internal memory: 1. N/A 2. Value pushed
POP Rd	Internal memory: 1. Address of instruction 2. Address of next instruction	Internal memory: 1. N/A 2. Value popped	Internal memory: 1. N/A 2. Stack Pointer	Internal memory: 1. N/A 2. Value popped

Bit and Bit-test Instructions

Instruction PMem Addr Reg.Val Dat.Addr Dat.Val

LSL Rd Will never appear (is disassembled
to ADD instruction) N/A N/A N/A

LSR Rd Address of instruction Result of shift N/A N/A

ROL Rd Will never appear (is disassembled
to ADC instruction) N/A N/A N/A

ROR Rd Address of instruction Result of rotate N/A N/A

ASR Rd Address of instruction Result of shift N/A N/A

SWAP Rd Address of instruction Result of swap N/A N/A

BSET s Will never appear (is disassembled
to other SEflag instructions) N/A N/A N/A

BCLR s Will never appear (is disassembled
to other CLflag instructions) N/A N/A N/A

SBI A,b 1. Address of instruction
2. Address of next instruction 1. N/A
2. N/A 1. 5 LSB give I/O address (A)
2. 5 LSB give I/O address (A) 1. Value read from I/O
2. Value written to I/O

CBI A,b 1. Address of instruction
2. Address of next instruction 1. N/A
2. N/A 1. 5 LSB give I/O address (A)
2. 5 LSB give I/O address (A) 1. Value read from I/O
2. Value written to I/O

BST Rr,b Address of instruction N/A N/A N/A

BLD Rd,b Address of instruction The bit in the actual position
reflects the loaded bit value N/A N/A

SEC Address of instruction N/A N/A N/A

CLC Address of instruction N/A N/A N/A

SEN Address of instruction N/A N/A N/A

CLN Address of instruction N/A N/A N/A

SEZ Address of instruction N/A N/A N/A

CLZ Address of instruction N/A N/A N/A

SEI Address of instruction N/A N/A N/A

CLI Address of instruction N/A N/A N/A

SES Address of instruction N/A N/A N/A

CLN Address of instruction N/A N/A N/A

SEV Address of instruction N/A N/A N/A

CLV Address of instruction N/A N/A N/A

SET Address of instruction N/A N/A N/A

CLT Address of instruction N/A N/A N/A

SEH Address of instruction N/A N/A N/A

CLH Address of instruction N/A N/A N/A

NOP Address of instruction N/A N/A N/A

SLEEP Address of instruction N/A N/A N/A

WDR Address of instruction N/A N/A N/A

Instruction	PMem Addr	Reg.Val	Dat.Addr	Dat.Val
RJMP k	1. Address of instruction 2. N/A	1. N/A 2. N/A	1. N/A 2. N/A	1. N/A 2. N/A
IJMP	1. Address of instruction 2. N/A	1. N/A 2. N/A	1. N/A 2. Destination address	1. N/A 2. N/A
EIJMP	Currently not supported in Emulator	N/A	N/A	N/A
JMP k	1. Address of instruction 2. Address of address-part of instruction 3. N/A	1. N/A 2. N/A 3. N/A	1. N/A 2. N/A 3. N/A	1. N/A 2. N/A 3. N/A
RCALL k	Stack in internal memory: 1. Address of instruction 2. N/A 3. Address of RCALL destination	Stack in internal memory: 1. N/A 2. N/A 3. N/A	Stack in internal memory: 1. N/A 2. Stack Pointer 3. Stack Pointer	Stack in internal memory: 1. N/A 2. Return address, low byte 3. Return address, high byte
ICALL	Stack in internal memory: 1. Address of instruction 2. N/A 3. Address of ICALL destination	Stack in internal memory: 1. N/A 2. N/A 3. N/A	Stack in internal memory: 1. N/A 2. Stack Pointer 3. Stack Pointer	Stack in internal memory: 1. N/A 2. Return address, low byte 3. Return address, high byte
EICALL	Currently not supported in Emulator	N/A	N/A	N/A
CALL k	Stack in internal memory: 1. Address of instruction 2. Address of address-part of instruction 3. N/A 4. Address of CALL destination	Stack in internal memory: 1. N/A 2. N/A 3. N/A 4. N/A	Stack in internal memory: 1. N/A 2. N/A 3. Stack Pointer 4. Stack Pointer	Stack in internal memory: 1. N/A 2. N/A 3. Return address, low byte 4. Return address, high byte
RET	Stack in internal memory: 1. Address of instruction 2. N/A 3. N/A 4. N/A	Stack in internal memory: 1. N/A 2. N/A 3. N/A 4. N/A	Stack in internal memory: 1. N/A 2. Stack Pointer 3. Stack Pointer 4. N/A	Stack in internal memory: 1. N/A 2. Return address, high byte 3. Return address, low byte 4. N/A
RETI	Stack in internal memory: 1. Address of instruction 2. N/A 3. N/A 4. N/A	Stack in internal memory: 1. N/A 2. N/A 3. N/A 4. N/A	Stack in internal memory: 1. N/A 2. Stack Pointer 3. Stack Pointer 4. N/A	Stack in internal memory: 1. N/A 2. Return address, high byte 3. Return address, low byte 4. N/A
CPSE Rd,Rr	Condition not met (no skip) 1. Address of instruction Condition met, skipping 1 word instruction 1. Address of instruction 2. Address of skipped instruction Condition met, skipping 2 word instruction 1. Address of instruction 2. Address of skipped instruction, first word 3. Address of skipped instruction, second word	Condition not met (no skip) 1. N/A Condition met, skipping 1 word instruction 1. N/A 2. N/A Condition met, skipping 2 word instruction 1. N/A 2. N/A 3. N/A	Condition not met (no skip) 1. N/A Condition met, skipping 1 word instruction 1. N/A 2. N/A Condition met, skipping 2 word instruction 1. N/A 2. N/A 3. N/A	Condition not met (no skip) 1. N/A Condition met, skipping 1 word instruction 1. N/A 2. N/A Condition met, skipping 2 word instruction 1. N/A 2. N/A 3. N/A
CP Rd,Rr	Address of instruction	N/A	N/A	N/A
CPC Rd,Rr	Address of instruction	N/A	N/A	N/A
CPI Rd,K	Address of instruction	N/A	N/A	N/A
SBRC Rr,b	Condition not met (no skip) 1. Address of instruction Condition met, skipping 1 word instruction 1. Address of instruction 2. Address of skipped instruction Condition met, skipping 2 word instruction 1. Address of instruction 2. Address of skipped instruction, first word 3. Address of skipped instruction, second word	Condition not met (no skip) 1. Value of register Condition met, skipping 1 word instruction 1. Value of register 2. N/A Condition met, skipping 2 word instruction 1. Value of register 2. N/A 3. N/A	Condition not met (no skip) 1. N/A Condition met, skipping 1 word instruction 1. N/A 2. N/A Condition met, skipping 2 word instruction 1. N/A 2. N/A 3. N/A	Condition not met (no skip) 1. N/A Condition met, skipping 1 word instruction 1. N/A 2. N/A Condition met, skipping 2 word instruction 1. N/A 2. N/A 3. N/A
SBRS Rr,b	Condition not met (no skip) 1. Address of instruction Condition met, skipping 1 word instruction 1. Address of instruction 2. Address of skipped instruction Condition met, skipping 2 word instruction 1. Address of instruction 2. Address of skipped instruction, first word 3. Address of skipped instruction, second word	Condition not met (no skip) 1. Value of register Condition met, skipping 1 word instruction 1. Value of register 2. N/A Condition met, skipping 2 word instruction 1. Value of register 2. N/A 3. N/A	Condition not met (no skip) 1. N/A Condition met, skipping 1 word instruction 1. N/A 2. N/A Condition met, skipping 2 word instruction 1. N/A 2. N/A 3. N/A	Condition not met (no skip) 1. N/A Condition met, skipping 1 word instruction 1. N/A 2. N/A Condition met, skipping 2 word instruction 1. N/A 2. N/A 3. N/A
SBIC A,b	Condition not met (no skip) 1. Address of instruction Condition met, skipping 1 word instruction 1. Address of instruction 2. Address of skipped instruction Condition met, skipping 2 word instruction 1. Address of instruction 2. Address of skipped instruction, first word 3. Address of skipped instruction, second word	Condition not met (no skip) 1. N/A Condition met, skipping 1 word instruction 1. N/A 2. N/A Condition met, skipping 2 word instruction 1. N/A 2. N/A 3. N/A	Condition not met (no skip) 1. 5 LSB give I/O address (A) Condition met, skipping 1 word instruction 1. 5 LSB give I/O address (A) 2. N/A Condition met, skipping 2 word instruction 1. 5 LSB give I/O address (A) 2. N/A 3. N/A	Condition not met (no skip) 1. N/A Condition met, skipping 1 word instruction 1. N/A 2. N/A Condition met, skipping 2 word instruction 1. N/A 2. N/A 3. N/A
SBIS A,b	Condition not met (no skip) 1. Address of instruction Condition met, skipping 1 word instruction 1. Address of instruction 2. Address of skipped instruction Condition met, skipping 2 word instruction 1. Address of instruction 2. Address of skipped instruction, first word 3. Address of skipped instruction, second word	Condition not met (no skip) 1. N/A Condition met, skipping 1 word instruction 1. N/A 2. N/A Condition met, skipping 2 word instruction 1. N/A 2. N/A 3. N/A	Condition not met (no skip) 1. 5 LSB give I/O address (A) Condition met, skipping 1 word instruction 1. 5 LSB give I/O address (A) 2. N/A Condition met, skipping 2 word instruction 1. 5 LSB give I/O address (A) 2. N/A 3. N/A	Condition not met (no skip) 1. N/A Condition met, skipping 1 word instruction 1. N/A 2. N/A Condition met, skipping 2 word instruction 1. N/A 2. N/A 3. N/A
BRBC s,k	Will never appear (is disassembled to other branch instructions)	N/A	N/A	N/A
BRBS s,k	Will never appear (is disassembled to other branch instructions)	N/A	N/A	N/A
BREQ k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRNE k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRCS k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRCC k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRSH k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRLO k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRMI k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRPL k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRGE k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRLT k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRHS k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRHC k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRTS k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRTC k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRVS k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRVC k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRIE k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A
BRID k	Branch not taken: 1. Address of instruction Branch taken: 1. Address of instruction 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A	Branch not taken: 1. N/A Branch taken: 1. N/A 2. N/A

Instruction	PMem Addr	Reg.Val	Dat.Addr	Dat.Val
LSL Rd	Will never appear (is disassembled to ADD instruction)	N/A	N/A	N/A
LSR Rd	Address of instruction	Result of shift	N/A	N/A
ROL Rd	Will never appear (is disassembled to ADC instruction)	N/A	N/A	N/A
ROR Rd	Address of instruction	Result of rotate	N/A	N/A
ASR Rd	Address of instruction	Result of shift	N/A	N/A
SWAP Rd	Address of instruction	Result of swap	N/A	N/A
BSET s	Will never appear (is disassembled to other SEflag instructions)	N/A	N/A	N/A
BCLR s	Will never appear (is disassembled to other CLflag instructions)	N/A	N/A	N/A
SBI A,b	1. Address of instruction 2. Address of next instruction	1. N/A 2. N/A	1. 5 LSB give I/O address (A) 2. 5 LSB give I/O address (A)	1. Value read from I/O 2. Value written to I/O
CBI A,b	1. Address of instruction 2. Address of next instruction	1. N/A 2. N/A	1. 5 LSB give I/O address (A) 2. 5 LSB give I/O address (A)	1. Value read from I/O 2. Value written to I/O
BST Rr,b	Address of instruction	N/A	N/A	N/A
BLD Rd,b	Address of instruction	The bit in the actual position reflects the loaded bit value	N/A	N/A
SEC	Address of instruction	N/A	N/A	N/A
CLC	Address of instruction	N/A	N/A	N/A
SEN	Address of instruction	N/A	N/A	N/A
CLN	Address of instruction	N/A	N/A	N/A
SEZ	Address of instruction	N/A	N/A	N/A
CLZ	Address of instruction	N/A	N/A	N/A
SEI	Address of instruction	N/A	N/A	N/A
CLI	Address of instruction	N/A	N/A	N/A
SES	Address of instruction	N/A	N/A	N/A
CLN	Address of instruction	N/A	N/A	N/A
SEV	Address of instruction	N/A	N/A	N/A
CLV	Address of instruction	N/A	N/A	N/A
SET	Address of instruction	N/A	N/A	N/A
CLT	Address of instruction	N/A	N/A	N/A
SEH	Address of instruction	N/A	N/A	N/A
CLH	Address of instruction	N/A	N/A	N/A
NOP	Address of instruction	N/A	N/A	N/A
SLEEP	Address of instruction	N/A	N/A	N/A
WDR	Address of instruction	N/A	N/A	N/A